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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDPFR, External Debug Processor Feature Register</h1><p>The EDPFR characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about implemented PE features.</p>

      
        <p>For general information about the interpretation of the ID registers, see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>The power domain of EDPFR is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><h2>Attributes</h2>
        <p>EDPFR is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-63_60-1">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-59_56-1">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-55_52">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-51_48-1">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-47_44">AMU</a></td><td class="lr" colspan="4"><a href="#fieldset_0-43_40-1">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-39_36">SEL2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-35_32">SVE</a></td></tr><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28-1">UNKNOWN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">GIC</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">AdvSIMD</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">FP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">EL3</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">EL2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">EL1</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">EL0</a></td></tr></tbody></table><h4 id="fieldset_0-63_60-1">Bits [63:60]<span class="condition"><br/>From Armv8.5:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-63_60-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-59_56-1">Bits [59:56]<span class="condition"><br/>From Armv8.5:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-59_56-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-55_52">Bits [55:52]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-51_48-1">Bits [51:48]<span class="condition"><br/>From Armv8.4:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-51_48-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-47_44">AMU, bits [47:44]</h4><div class="field">
      <p>Indicates support for Activity Monitors Extension. Defined values are:</p>
    <table class="valuetable"><tr><th>AMU</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Activity Monitors Extension is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p><span class="xref">FEAT_AMUv1</span> is implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p><span class="xref">FEAT_AMUv1p1</span> is implemented. As <span class="binarynumber">0b0001</span> and adds support for virtualization of the activity monitor event counters.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_AMUv1</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p><span class="xref">FEAT_AMUv1p1</span> implements the functionality identified by the value <span class="binarynumber">0b0010</span>.</p>
<p>In Armv8.0, the only permitted value is <span class="binarynumber">0b0000</span>.</p>
<p>In Armv8.4, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.6, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-43_40-1">Bits [43:40]<span class="condition"><br/>From Armv8.2:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-43_40-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_36">SEL2, bits [39:36]</h4><div class="field">
      <p>Secure EL2. Defined values are:</p>
    <table class="valuetable"><tr><th>SEL2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Secure EL2 is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Secure EL2 is implemented.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-35_32">SVE, bits [35:32]</h4><div class="field">
      <p>Scalable Vector Extension. Defined values are:</p>
    <table class="valuetable"><tr><th>SVE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>SVE is not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>SVE is implemented.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-31_28-1">Bits [31:28]<span class="condition"><br/>From Armv8.2:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">UNKNOWN</span>.</p>
    </div><h4 id="fieldset_0-31_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-27_24">GIC, bits [27:24]</h4><div class="field">
      <p>System register GIC interface support. Defined values are:</p>
    <table class="valuetable"><tr><th>GIC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>GIC CPU interface system registers not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>System register interface to version 4.1 of the GIC CPU interface is supported.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.GIC.</p></div><h4 id="fieldset_0-23_20">AdvSIMD, bits [23:20]</h4><div class="field">
      <p>Advanced SIMD. Defined values are:</p>
    <table class="valuetable"><tr><th>AdvSIMD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td><p>Advanced SIMD is implemented, including support for the following SISD and SIMD operations:</p>
<ul>
<li>Integer byte, halfword, word and doubleword element operations.
</li><li>Single-precision and double-precision floating-point arithmetic.
</li><li>Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
</li></ul></td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>As for <span class="binarynumber">0b0000</span>, and also includes support for half-precision floating-point arithmetic.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Advanced SIMD is not implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field must have the same value as the FP field.</p>
<p>The permitted values are:</p>
<ul>
<li><span class="binarynumber">0b0000</span> in an implementation with Advanced SIMD support, that does not include the <span class="xref">FEAT_FP16</span> extension.
</li><li><span class="binarynumber">0b0001</span> in an implementation with Advanced SIMD support, that includes the <span class="xref">FEAT_FP16</span> extension.
</li><li><span class="binarynumber">0b1111</span> in an implementation without Advanced SIMD support.
</li></ul>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.AdvSIMD.</p></div><h4 id="fieldset_0-19_16">FP, bits [19:16]</h4><div class="field">
      <p>Floating-point. Defined values are:</p>
    <table class="valuetable"><tr><th>FP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td><p>Floating-point is implemented, and includes support for:</p>
<ul>
<li>Single-precision and double-precision floating-point types.
</li><li>Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
</li></ul></td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>As for <span class="binarynumber">0b0000</span>, and also includes support for half-precision floating-point arithmetic.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Floating-point is not implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field must have the same value as the AdvSIMD field.</p>
<p>The permitted values are:</p>
<ul>
<li><span class="binarynumber">0b0000</span> in an implementation with floating-point support, that does not include the <span class="xref">FEAT_FP16</span> extension.
</li><li><span class="binarynumber">0b0001</span> in an implementation with floating-point support, that includes the <span class="xref">FEAT_FP16</span> extension.
</li><li><span class="binarynumber">0b1111</span> in an implementation without floating-point support.
</li></ul>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.FP.</p></div><h4 id="fieldset_0-15_12">EL3, bits [15:12]</h4><div class="field">
      <p>AArch64 EL3 Exception level handling. Defined values are:</p>
    <table class="valuetable"><tr><th>EL3</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>EL3 is not implemented or cannot be executed in AArch64 state.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>EL3 can be executed in AArch64 state only.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>EL3 can be executed in both Execution states.</p>
        </td></tr></table><p>When the value of <a href="ext-edaa32pfr.html">EDAA32PFR</a>.EL3 is nonzero, this field must be <span class="binarynumber">0b0000</span>.</p>
<p>All other values are reserved.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.EL3.</p></div><h4 id="fieldset_0-11_8">EL2, bits [11:8]</h4><div class="field">
      <p>AArch64 EL2 Exception level handling. Defined values are:</p>
    <table class="valuetable"><tr><th>EL2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>EL2 is not implemented or cannot be executed in AArch64 state.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>EL2 can be executed in AArch64 state only.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>EL2 can be executed in both Execution states.</p>
        </td></tr></table><p>When the value of <a href="ext-edaa32pfr.html">EDAA32PFR</a>.EL2 is nonzero, this field must be <span class="binarynumber">0b0000</span>.</p>
<p>All other values are reserved.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.EL2.</p></div><h4 id="fieldset_0-7_4">EL1, bits [7:4]</h4><div class="field">
      <p>AArch64 EL1 Exception level handling. Defined values are:</p>
    <table class="valuetable"><tr><th>EL1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td><p>EL1 cannot be executed in AArch64 state.</p>
<p>EL1 can be executed in AArch32 state only.</p></td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>EL1 can be executed in AArch64 state only.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>EL1 can be executed in both Execution states.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.EL1.</p></div><h4 id="fieldset_0-3_0">EL0, bits [3:0]</h4><div class="field">
      <p>AArch64 EL0 Exception level handling. Defined values are:</p>
    <table class="valuetable"><tr><th>EL0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td><p>EL0 cannot be executed in AArch64 state.</p>
<p>EL0 can be executed in AArch32 state only.</p></td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>EL0 can be executed in AArch64 state only.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>EL0 can be executed in both Execution states.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In an Armv8-A implementation that supports AArch64, this field returns the value of <a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>.EL0.</p></div><h2>Accessing EDPFR</h2><h4>EDPFR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0xD20</span></td><td>EDPFR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered() and !DoubleLockStatus(), accesses to this register are <span class="access_level">RO</span>.
          </li><li>Otherwise, accesses to this register are <span class="access_level">IMPDEF</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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